Stavros Kalapothas

PhD researcher, Member of the Electronic Circuits, Systems and Applications (@ECSAlab) Laboratory

My Projects

GitHub repositories that I've built.

1D Median Filter in ARM Assembly
HTML 1 0
A UART Tx/Rx Module in VHDL
VHDL 1 0
An example for NIOS II processor to toggle a Led with a Button
Verilog 1 0
A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
VHDL 1 0
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
VHDL 2 0
A 4bit Multiplier in VHDL
VHDL 1 0
An Ansible playbook to configure a CentOS/RHEL/Oracle Linux 7 server with Oracle Fusion Middleware 12.2.1.3
Python 10 24

My Interests

Research areas that I focus.